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Hello! I'm TR of R&D department.
In this article, We would like to talk about the development of our plating technology that realizes the formation of through silicon vias (TSVs), which is a key technology for next-generation electronic devices, at low cost.
Through Silicon Via (TSV), a technology required to minimize the wiring distance between chips
IoT (Internet of Things), which connects things to each other via the Internet, is progressing in various fields such as next-generation high-speed communication (5G), industries, automobiles, transportation systems and security. The electronic devices that make up the IoT are required to save energy, process large amounts of data, and have low latency. To meet these demands, the wiring between the chips must be as short as possible.
Through Silicon Via (TSV) is a technology that can minimize the wiring distance between chips. It is used for stacking DRAMs and silicon interposers (2.5D stacking) that connect chips such as memory and logic on silicon wafers. However, the equipment cost and production cost are high and it is only used in a small number of electronic devices.
Currently, TSV formation technology and alternative technologies that can be realized at low cost are being actively developed and are expected to be applied to IoT devices for integrations of heterogeneous devices such as various sensors and RF front-end modules are stacked in three dimensions in the future.
Development of face-up automatic plating equipment for 12-inch wafers
We have been working on the development of face-up automatic plating tool for 12-inch wafers through the SAPOIN (supporting industry) business adopted by the Ministry of Economy, Trade and Industry(METI) in 2014 for TSV formation technology that can be realized at low cost.
The face-up plating tool has a high in-plane film thickness uniformity and the wafer surface faces upward, so it has the advantage that air bubbles do not easily remain in the holes and is suitable for TSVs, trenches and via filling.
Also, for the formation of the barrier and seed layers required for copper electroplating to form TSV, a sputtering tool is usually used, but depending on the size of the TSV, the technical hurdles and costs will change. If the aspect ratio exceeds 10, the coverage of via bottom get worse. The risk of copper plating failure will be getting high. CVD and ALD are the alternative processes that enable uniform deposition inside vias, but they are costly.
Therefore, we are proceeding with process development and equipment development for the technology to form the barrier and seed layers by electroless plating. In TSV with high aspect ratio, uniform film formation is possible and process cost can be reduced compared to sputtering.
Support by Tosetz for customer’s research and development
We are accepting demo evaluations of copper plating from manufacturers related to electronic devices and sensors for the purpose of developing new products and evaluation of the installation of production equipment. We have a CVS(cyclic voltammetry stripping) analyzer and a cross-section grinding machine in-house, and we have prepared an environment for basic evaluation of TSV, via filling, and through-hole plating.
Normally, we receive test samples such as silicon, glass, and organic substrate from our customers to evaluate the plating process. If necessary, we can prepare dedicated plating jigs or we can procure test samples cooperated with wafer processing manufacturer.
We also propose production equipment suitable for the required process conditions, and design and manufacture plating experimental machines for our customers.
Lastly
What do you think?
Tosetz’ process engineers with abundant experience in TSV, via filling, and through-hole plating will support your research and development!
Click here if you are interested in Tosetz.
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